IC2251 Digital Principles and Design 2 marks important questions with answers:-
Anna University Chennai
Digital Logic Circuits (EI2253)
(2marks)
Unit – 1
1) Define binary logic?
Binary logic consists of binary variables and logical operations. The variables are designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having only two distinct values: 1 and 0.
There are three basic logic operations:
(i) AND (ii) OR (iii) NOT.
2) Write the names of basic logical operators.
1. NOT / INVERT
2. AND
3. OR
3) What are basic properties of Boolean algebra?
The basic properties of Boolean algebra are commutative property, associative property and distributive property.
4) State the associative property of Boolean algebra.
The associative property of Boolean algebra states that the OR ing of several variables results in the same regardless of the grouping of the variables. The associative property is stated as follows:
A+ (B+C) = (A+B) +C
5) State the commutative property of Boolean algebra.
The commutative property states that the order in which the variables are OR ed makes no difference. The commutative property is: A+B=B+A
6) State the distributive property of Boolean algebra.
The distributive property states that AND ing several variables and OR ing the result with a single variable is equivalent to OR ing the single variable with each of the several variables and then AND ing the sums. The distributive property is: A+BC= (A+B) (A+C)
7) State the absorption law of Boolean algebra.
The absorption law of Boolean algebra is given by: X+XY=Xand X(X+Y) =X
8) Simplify the following using De Morgan's theorem [((AB) 'C)'' D]'
[(( AB)'C)'' D]' = ((AB)'C)'' + D' [(AB)' = A' + B'] = (AB)' C + D' = (A' + B‟) C + D'
9) State De Morgan's theorem.
De Morgan suggested two theorems that form important part of Boolean algebra. They are,
1) The complement of a product is equal to the sum of the complements. (AB)' = A' + B'
2) The complement of a sum term is equal to the product of the complements. (A + B)' = A'B'
10) Reduce A.A'C
A.A'C = 0.C (...[A.A' = 1] ) = 0
11) Reduce A ( A + B)
A (A + B) = AA + AB
= A (1 + B)
= A(...[1 + B = 1])
12) Reduce A'B'C' + A'BC' + A'BC
A'B'C' + A'BC' + A'BC = A'C'(B' + B) + A'B'C
= A'C' + A'BC [A + A' = 1]
= A'(C' + BC)
= A'(C' + B) [A + A'B = A + B]
13) Reduce AB + (AC)' + AB’C (AB + C)
AB + (AC)' + AB‟C (AB + C) = AB + (AC)' + AAB'BC + AB'CC
= AB + (AC) ' + AB'CC [A.A' = 0]
= AB + (AC) ' + AB'C [A.A = 1]
= AB + A' + C' =AB'C [(AB)' = A' + B']
= A' + B + C' + AB'C [A + AB' = A + B]
= A' + B'C + B + C' [A + A'B = A + B]
= A' + B + C' + B'C
=A' + B + C' + B'
=A' + C' + 1
= 1 [A + 1 =1]
14) Simplify the following expression Y = (A + B)(A + C' )(B' + C' )
Y = (A + B)(A + C' )( B' + C' )
= (AA' + AC +A'B +BC) (B' + C') [A.A' = 0]
= (AC + A'B + BC) (B' + C‟)
= AB'C + ACC' + A'BB' + A'BC' + BB'C + BCC'
= AB'C + A'BC'
15) Show that (X + Y' + XY) (X + Y') (X'Y) = 0
(X + Y' + XY)(X + Y')(X'Y) = (X + Y' + X) (X + Y‟) (X' + Y) [A + A'B = A + B]
= (X + Y‟) (X + Y‟) (X'Y) [A + A = 1]
= (X + Y‟) (X'Y) [A.A = 1]
= X.X' + Y'.X'.Y
= 0 [A.A' = 0]
16) Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC
ABC + ABC' + AB'C + A'BC=AB( C + C') + AB'C + A'BC
=AB + AB'C + A'BC
=A (B + B'C) + A'BC
=A (B + C) + A'BC
=AB + AC + A'BC
=B (A + C) + AC
=AB + BC + AC
=AB + AC +BC ...Proved
17) Convert the given expression in canonical SOP form Y = AC + AB +BC
Y = AC + AB + BC
=AC (B + B‟) + AB (C + C‟) + (A + A') BC
=ABC + ABC' + AB'C + AB'C' + ABC + ABC' + ABC
=ABC + ABC' +AB'C + AB'C' [A + A =1]
18) Define duality property.
Duality property states that every algebraic expression deducible from the postulates of Boolean algebra remains valid if the operators and identity elements are interchanged. If the dual of an algebraic expression is desired, we simply interchange OR and AND operators and replace 1's by 0's and 0's by 1's.
19) Find the complement of the functions
F1 = x'yz' + x'y'z and F2 = x (y'z' + yz),by applying De-Morgan's theorem.
F1' = (x'yz' + x'y'z)' = (x'yz') '(x'y'z)' = (x + y' + z)(x + y +z')
F2' = [x(y'z' + yz)]' = x' + (y'z' + yz)'
= x' + (y'z')'(yz)'
= x' + (y + z)(y' + z')
20) Simplify the following expression
Y = (A + B) (A = C) (B + C)
= (A A + A C + A B + B C) (B + C)
= (A C + A B + B C) (B + C)
= A B C + A C C + A B B + A B C + B B C + B C C
= A B C
1) Synchronous sequential circuit. 2)Asynchronous sequential circuit.
2. Define Flip flop.
The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state.
3. What are the different types of flip-flop?
There are various types of flip flops. Some of them are mentioned below they are,
RS flip-flop
SR flip-flop
D flip-flop
JK flip-flop
T flip-flop
4. What is the operation of RS flip- flop?
When R input is low and S input is high the Q output of flip-flop is set.
When R input is high and S input is low the Q output of flip-flop is reset.
When both the inputs R and S are low the output does not change
When both the inputs R and S are high the output is unpredictable.
5. What is the operation of SR flip- flop?
1. When R input is low and S input is high the Q output of flip-flop is set.
2. When R input is high and S input is low the Q output of flip-flop is reset.
3. When both the inputs R and S are low the output does not change.
4. When both the inputs R and S are high the output is unpredictable.
6. What is the operation of D flip-flop?
In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset.
7. What is the operation of JK flip-flop?
a) When K input is low and J input is high the Q output of flip-flop is set.
b) When K input is high and J input is low the Q output of flip-flop is reset.
c) When both the inputs K and J are low the output does not change
d) When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the output toggle on the next positive clock edge.
8. What is the operation of T flip-flop?
T flip-flop is also known as Toggle flip- flop.
When T=0 there is no change in the output.
When T=1 the output switch to the complement state (ie) the output toggles.
9. Define race around condition.
In JK flip-flop output is fed back to the input. Therefor e change in the output results change in the input. Due to this in the positive half of the clock pulse if both J and K are high then output toggles continuously. This condition is called “race around condition”.
10. What is edge-triggered flip- flop?
The problem of race around condition can solved by edge triggering flip flop. The term edge triggering means that the flip-flop changes state either at the positive edge or negative edge of the clock pulse and it is sensitive to its inputs only at this transition of the clock.
11. What is a master-slave flip-flop?
A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave.
12. Define rise time.
The time required to change the voltage level from 10% to 90% is known as rise time (tr).
13. Define fall time.
The time required to change the voltage level from 90% to 10% is known as fall time (tf).
14. Define propagation delay.
A propagation delay is the time required to change the output after the application of the input.
15. Explain the flip- flop excitation tables for RS FF.
In RS flip-flop there are four possible transitions from the present state to the next state. They are,
00 transition: This can happen either when R=S=0 or when R=1 and S=0.
01 transition: This can happen only when S=1 and R=0.
10 transition: This can happen only when S=0 and R=1.
11 transition: This can happen either when S=1 and R=0 or S=0 and R=0.
16. Explain the flip- flop excitation tables for JK flip-flop
In JK flip-flop also there are four possible transitions from present state to next state. They are,
00 transition: This can happen when J=0 and K=1 or K=0.
01 transition: This can happen either when J=1 and K=0 or when J=K=1.
10 transition: This can happen either when J=0 and K=1 or when J=K=1.
11 transition: This can happen when K=0 and J=0 or J=1.
17. Explain the flip- flop excitation tables for D flip-flop
In D flip-flop the next state is always equal to the D input and it is independent of the present state. Therefore D must be 0 if Qn+1 have to 0, and if Qn+1 has to be 1 regardless the value of Qn.
18. Explain the flip- flop excitation tables for T flip-flop
When input T=1 the state of the flip- flop is complemented; when T=0,the state of the flip-flop remains unchanged. Therefore, for 0_0 and 1_1 transitions T must be 0 and for 0 1 and 1 0 transitions must be 1.
19. Define sequential circuit?
In sequential circuits the output variables dependent not only on the present input variables but they also depend up on the past history of these input variables.
20. Give the comparison between combinational circuits and sequential circuits.
S.No Combinational circuits Sequential circuits
1 Memory unit is not required Memory unity is required
2 Parallel adder is a combinational circuit Serial adder is a sequential circuit
Unit III
1. What are secondary variables?
Present state variables in asynchronous sequential circuits.
2. What are excitation variables?
Next state variables in asynchronous sequential circuits.
3. What is fundamental mode sequential circuit?
-input variables changes if the circuit is stable
-inputs are levels, not pulses
-only one input can change at a given time
4. What is pulse mode circuit?
-inputs are pulses
-widths of pulses are long for circuit to respond to the input -pulse width must not be so long that it is still present after the new state is reached
5. What is the significance of state assignment?
In synchronous circuits-state assignments are made with the objective of circuit reduction In Asynchronous circuits-its objective is to avoid critical races.
6. When does race condition occur?
Two or more binary state variables change their value in response to the change in i/p variable.
7. What is non-critical race?
-final stable state does not depend on the order in which the state variable changes. -race condition is not harmful
8. What is critical race?
-final stable state depends on the order in which the state variable changes
-race condition is harmful
9. When does a cycle occur?
Asynchronous circuit makes a transition through a series of unstable state.
10. What are the different techniques used in state assignment?
-shared row state assignment -One hot state assignment
11. What are the steps for the design of asynchronous sequential circuit?
-construction of primitive flow table
-reduction of flow table
-state assignment is made
-realization of primitive flow table
12. What is flow table?
It is defined as the state table of a synchronous sequential network.
13. What is primitive flow chart?
One stable state per row.
14. What is combinational circuit?
Output depends on the given input. It has no storage element.
15. What is state equivalence theorem?
Two states SA and SB are equivalent if and only if for every possible input X sequence, the outputs are the same and the next states are equivalent i.e., if SA ( t + 1) = SB (t + 1) and ZA = ZB then SA = SB.
16. What do you mean by distinguishing sequences?
Two states, SA and SB of sequential machine are distinguishable if and only if there exists at least one finite input sequence. Which, when applied to sequential machine causes different output sequences depending on whether SA or SB is the initial state.
17. Prove that the equivalence partition is unique.
Consider that there are two equivalence partitions exist: PA and PB, and PA PB. This states that, there exist 2 states Si &Sj which are in the same block of one partition and not in the same block of the other. If Si &Sj are in different blocks of say PB, there exists atleast on inputsequence which distinguishes Si &Sj and therefore, they cannot be in the same block of PA.
18. Define merger graph.
The merger graph is defined as follows. It contains the same number of vertices as the state table contains states. A line drawn between the two state vertices indicates each compatible state pair. It two states are incompatible no connecting line is drawn.
19. Explain the procedure for state minimization.
a. Partition the states into subsets such that all states in the same subsets are 1 -equivalent.
b. Partition the states into subsets such that all states in the same subsets are 2 -equivalent.
c. Partition the states into subsets such that all states in the same subsets are 3 -equivalent.
20. Define closed covering.
A Set of compatibles is said to be closed if, for every compatible contained in the set, all its implied compatibles are also contained in the set. A closed set of compatibles, which contains all the states of M, is called a closed covering.
Unit – IV
1. What is a Logic gate?
Logic gates are the basic elements that make up a digital system. The electronic gate is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical function.
2. Give the classification of logic families
1. Bipolar Unipolar
2. Saturated Non Saturated PMOS
3. NMOS
4. CMOS
5. RTL Schottky TTL
6. ECL DTL
7. TTL
8. I I C
3. What are the basic digital logic gates?
The three basic logic gates are:
AND gate
OR gate
NOT gate
4. Classify the logic family by operation?
The Bipolar logic family is classified into a) Saturatedlogic b) Unsaturated logic
The RTL, DTL, TTL, I2L, HTL logic comes under the saturated logic family.
The SchottkyTTL, and ECL logic comes under the unsaturated logic family.
5. State the classifications of FET devices.
FET is classified as
Junction Field Effect Transistor (JFET)
Metal oxide semiconductor family (MOS).
6. Mention the classification of saturated bipolar logic families.
The bipolar logic family is classified as follows:
1. RTL- Resistor Transistor Logic
2. DTL- Diode Transistor logic
3. I2L- Integrated Injection Logic
4. TTL- Transistor Transistor Logic
5. ECL- Emitter Coupled Logic
7. Mention the important characteristics of digital IC’s?
1. Fan out
2. Power dissipation
3. Propagation Delay
4. Noise Margin
5. Fan In
6. Operating temperature
7. Power supply requirements
8. Define Fan-out?
Fan out specifies the number of standard loads that the output of the gate can drive without impairment of its normal operation.
9. Define power dissipation?
Power dissipation is measure of power consumed by the gate when fully driven by all its inputs.
10. What is propagation delay?
Propagation delay is the average transition delay time for the signal to propagate from input to output when the signals change in value. It is expressed in NS.
11. Define noise margin?
It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an undesirable change in the circuit output. It is expressed in volts.
12. Define fan in?
Fan in is the number of inputs connected to the gate without any degradation in the voltage level.
13. What is Operating temperature?
All the gates or semiconductor devices are temperature sensitive in nature. The temperature in which the performance of the IC is effective is called as operating temperature. Operating temperature of the IC vary from 00 C to 700 c.
14. What is High Threshold Logic?
Some digital circuits operate in environments, which produce very high noise signals. For operation in such surroundings there is available a type of DTL gate which possesses a high threshold to noise immunity. This type of gate is called HTL logic or High Threshold Logic.
15. What are the types of TTL logic?
1. Open collector output
2. Totem-Pole Output
3. Tri-state output.
16. What is depletion mode operation MOS?
If the channel is initially doped lightly with p-type impurity a conducting channel exists at zero gate voltage and the device is said to operate in depletion mode.
17. What is enhancement mode operation of MOS?
If the region beneath the gate is left initially uncharged the gate field must induce a channel before current can flow. Thus the gate voltage enhances the channel current and such a device is said to operate in the enhancement mode.
18. Mention the characteristics of MOS transistor?
The n- channel MOS conducts when its gate- to- source voltage is positive.
The p- channel MOS conducts when its gate- to- source voltage is negative.
Either type of device is turned of if its gate- to- source voltage is zero.
19. How Schottky transistors are formed and state its use?
A schottky diode is formed by the combination of metal and semiconductor. The presence of Schottky diode between the base and the collector prevents the transistor from going into saturation. The resulting transistor is called as schottky transistor. The use of schottky transistor in TTL decreases the propagation delay without a sacrifice of power dissipation.
20. List the different versions of TTL
1. TTL (Std.TTL) 2.LTTL (Low Power TTL)
3. HTTL (High Speed TTL) 4.STTL (Schottky TTL)
5. LSTTL (Low power Schottky TTL)
UNIT V
1. List basic types of programmable logic devices.
a. Read only memory
b. Programmable logic Array
c. Programmable Array Logic
2. Define ROM
A read only memory is a device that includes both the decoder and the OR gates within a single IC package.
3. Define address and word:
In a ROM, each bit combination of the input variable is called on address. Each bit combination that comes out of the output lines is called a word.
4. What are the types of ROM?
a. Masked ROM.
b. Programmable Read only Memory
c. Erasable Programmable Read only memory.
d. Electrically Erasable Programmable Read only Memory.
5. What is programmable logic array? How it differs from ROM?
In some cases the number of don’t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM.
6. What is mask - programmable?
With a mask programmable PLA, the user must submit a PLA program table to the manufacturer.
7. What is field programmable gate array?
The second type of PLA is called a field programmable gate array. The EPLA can be programmed by the user by means of certain recommended procedures.
8. Give the comparison between prom and PLA.
S.No PROM PLA
1 And array is fixed and OR
array is programmable
Both AND and OR arrays are programmable.
2 Cheaper and simple to use Costliest and complex than PROMS
9. Define PROM.
PROM is Programmable Read Only Memory. It consists of a set of fixed AND gates connected to a decoder and a programmable OR array.
10. Define PLA
PLA is Programmable Logic Array (PLA). The PLA is a PLD that consists of a programmable AND array and a programmable OR array.
11. Define PAL
PAL is Programmable Array Logic. PAL consists of a programmable AND array and a fixed OR array with output logic.
12. Why was PAL developed?
It is a PLD that was developed to overcome certain disadvantages of PLA, such as longer delays due to additional fusible links that result from using two programmable arrays and more circuit complexity.
13. Why the input variables to a PAL are buffered
The input variables to a PAL are buffered to prevent loading by the large number of AND gate inputs to which available or its complement can be connected.
14. What does PAL 10L8 specify?
PAL - Programmable Logic Array
10 - Ten inputs
L - Active LOW Output
8 - Eight Outputs
15. Why totem pole outputs cannot be connected together.
Totem pole outputs cannot be connected together because such a connection might produce excessive current and may result in damage to the devices.
16. State advantages and disadvantages of TTL
Advantages:
Easily compatible with other ICs
Low output impedance
Disadvantages:
Wired output capability is possible only with tristate and open collector types Special circuits in Circuit layout and system design are required.
17. When does the noise margin allow digital circuit s to function properly?
When noise voltages ar e within the limits of VNA (High State Noise Margin) and VNK for a particular logic family.
18. Define state table.
For the design of sequential counters we have to relate present states and next states. The table, which represents the relationship between present states and next states, is called state table.
19. Define total state
The combination of level signals that appear at the inputs and the outputs of the delays define what is called the total state of the circuit.
20. What are the steps for the design of asynchronous sequential circuit?
1. Construction of a primitive flow table from the problem statement.
2. Primitive flow table is reduced by eliminating redundant states using the state reduction.
3. State assignment is made
4. The primitive flow table is realized using appropriate logic elements.
Anna University Chennai
Digital Logic Circuits (EI2253)
(2marks)
Unit – 1
1) Define binary logic?
Binary logic consists of binary variables and logical operations. The variables are designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having only two distinct values: 1 and 0.
There are three basic logic operations:
(i) AND (ii) OR (iii) NOT.
2) Write the names of basic logical operators.
1. NOT / INVERT
2. AND
3. OR
3) What are basic properties of Boolean algebra?
The basic properties of Boolean algebra are commutative property, associative property and distributive property.
4) State the associative property of Boolean algebra.
The associative property of Boolean algebra states that the OR ing of several variables results in the same regardless of the grouping of the variables. The associative property is stated as follows:
A+ (B+C) = (A+B) +C
5) State the commutative property of Boolean algebra.
The commutative property states that the order in which the variables are OR ed makes no difference. The commutative property is: A+B=B+A
6) State the distributive property of Boolean algebra.
The distributive property states that AND ing several variables and OR ing the result with a single variable is equivalent to OR ing the single variable with each of the several variables and then AND ing the sums. The distributive property is: A+BC= (A+B) (A+C)
7) State the absorption law of Boolean algebra.
The absorption law of Boolean algebra is given by: X+XY=Xand X(X+Y) =X
8) Simplify the following using De Morgan's theorem [((AB) 'C)'' D]'
[(( AB)'C)'' D]' = ((AB)'C)'' + D' [(AB)' = A' + B'] = (AB)' C + D' = (A' + B‟) C + D'
9) State De Morgan's theorem.
De Morgan suggested two theorems that form important part of Boolean algebra. They are,
1) The complement of a product is equal to the sum of the complements. (AB)' = A' + B'
2) The complement of a sum term is equal to the product of the complements. (A + B)' = A'B'
10) Reduce A.A'C
A.A'C = 0.C (...[A.A' = 1] ) = 0
11) Reduce A ( A + B)
A (A + B) = AA + AB
= A (1 + B)
= A(...[1 + B = 1])
12) Reduce A'B'C' + A'BC' + A'BC
A'B'C' + A'BC' + A'BC = A'C'(B' + B) + A'B'C
= A'C' + A'BC [A + A' = 1]
= A'(C' + BC)
= A'(C' + B) [A + A'B = A + B]
13) Reduce AB + (AC)' + AB’C (AB + C)
AB + (AC)' + AB‟C (AB + C) = AB + (AC)' + AAB'BC + AB'CC
= AB + (AC) ' + AB'CC [A.A' = 0]
= AB + (AC) ' + AB'C [A.A = 1]
= AB + A' + C' =AB'C [(AB)' = A' + B']
= A' + B + C' + AB'C [A + AB' = A + B]
= A' + B'C + B + C' [A + A'B = A + B]
= A' + B + C' + B'C
=A' + B + C' + B'
=A' + C' + 1
= 1 [A + 1 =1]
14) Simplify the following expression Y = (A + B)(A + C' )(B' + C' )
Y = (A + B)(A + C' )( B' + C' )
= (AA' + AC +A'B +BC) (B' + C') [A.A' = 0]
= (AC + A'B + BC) (B' + C‟)
= AB'C + ACC' + A'BB' + A'BC' + BB'C + BCC'
= AB'C + A'BC'
15) Show that (X + Y' + XY) (X + Y') (X'Y) = 0
(X + Y' + XY)(X + Y')(X'Y) = (X + Y' + X) (X + Y‟) (X' + Y) [A + A'B = A + B]
= (X + Y‟) (X + Y‟) (X'Y) [A + A = 1]
= (X + Y‟) (X'Y) [A.A = 1]
= X.X' + Y'.X'.Y
= 0 [A.A' = 0]
16) Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC
ABC + ABC' + AB'C + A'BC=AB( C + C') + AB'C + A'BC
=AB + AB'C + A'BC
=A (B + B'C) + A'BC
=A (B + C) + A'BC
=AB + AC + A'BC
=B (A + C) + AC
=AB + BC + AC
=AB + AC +BC ...Proved
17) Convert the given expression in canonical SOP form Y = AC + AB +BC
Y = AC + AB + BC
=AC (B + B‟) + AB (C + C‟) + (A + A') BC
=ABC + ABC' + AB'C + AB'C' + ABC + ABC' + ABC
=ABC + ABC' +AB'C + AB'C' [A + A =1]
18) Define duality property.
Duality property states that every algebraic expression deducible from the postulates of Boolean algebra remains valid if the operators and identity elements are interchanged. If the dual of an algebraic expression is desired, we simply interchange OR and AND operators and replace 1's by 0's and 0's by 1's.
19) Find the complement of the functions
F1 = x'yz' + x'y'z and F2 = x (y'z' + yz),by applying De-Morgan's theorem.
F1' = (x'yz' + x'y'z)' = (x'yz') '(x'y'z)' = (x + y' + z)(x + y +z')
F2' = [x(y'z' + yz)]' = x' + (y'z' + yz)'
= x' + (y'z')'(yz)'
= x' + (y + z)(y' + z')
20) Simplify the following expression
Y = (A + B) (A = C) (B + C)
= (A A + A C + A B + B C) (B + C)
= (A C + A B + B C) (B + C)
= A B C + A C C + A B B + A B C + B B C + B C C
= A B C
Unit – II
1. What are the classifications of sequential circuits?
The sequential circuits are classified on the basis of timing of their signals into two types. They are,1) Synchronous sequential circuit. 2)Asynchronous sequential circuit.
2. Define Flip flop.
The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state.
3. What are the different types of flip-flop?
There are various types of flip flops. Some of them are mentioned below they are,
RS flip-flop
SR flip-flop
D flip-flop
JK flip-flop
T flip-flop
4. What is the operation of RS flip- flop?
When R input is low and S input is high the Q output of flip-flop is set.
When R input is high and S input is low the Q output of flip-flop is reset.
When both the inputs R and S are low the output does not change
When both the inputs R and S are high the output is unpredictable.
5. What is the operation of SR flip- flop?
1. When R input is low and S input is high the Q output of flip-flop is set.
2. When R input is high and S input is low the Q output of flip-flop is reset.
3. When both the inputs R and S are low the output does not change.
4. When both the inputs R and S are high the output is unpredictable.
6. What is the operation of D flip-flop?
In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset.
7. What is the operation of JK flip-flop?
a) When K input is low and J input is high the Q output of flip-flop is set.
b) When K input is high and J input is low the Q output of flip-flop is reset.
c) When both the inputs K and J are low the output does not change
d) When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the output toggle on the next positive clock edge.
8. What is the operation of T flip-flop?
T flip-flop is also known as Toggle flip- flop.
When T=0 there is no change in the output.
When T=1 the output switch to the complement state (ie) the output toggles.
9. Define race around condition.
In JK flip-flop output is fed back to the input. Therefor e change in the output results change in the input. Due to this in the positive half of the clock pulse if both J and K are high then output toggles continuously. This condition is called “race around condition”.
10. What is edge-triggered flip- flop?
The problem of race around condition can solved by edge triggering flip flop. The term edge triggering means that the flip-flop changes state either at the positive edge or negative edge of the clock pulse and it is sensitive to its inputs only at this transition of the clock.
11. What is a master-slave flip-flop?
A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave.
12. Define rise time.
The time required to change the voltage level from 10% to 90% is known as rise time (tr).
13. Define fall time.
The time required to change the voltage level from 90% to 10% is known as fall time (tf).
14. Define propagation delay.
A propagation delay is the time required to change the output after the application of the input.
15. Explain the flip- flop excitation tables for RS FF.
In RS flip-flop there are four possible transitions from the present state to the next state. They are,
00 transition: This can happen either when R=S=0 or when R=1 and S=0.
01 transition: This can happen only when S=1 and R=0.
10 transition: This can happen only when S=0 and R=1.
11 transition: This can happen either when S=1 and R=0 or S=0 and R=0.
16. Explain the flip- flop excitation tables for JK flip-flop
In JK flip-flop also there are four possible transitions from present state to next state. They are,
00 transition: This can happen when J=0 and K=1 or K=0.
01 transition: This can happen either when J=1 and K=0 or when J=K=1.
10 transition: This can happen either when J=0 and K=1 or when J=K=1.
11 transition: This can happen when K=0 and J=0 or J=1.
17. Explain the flip- flop excitation tables for D flip-flop
In D flip-flop the next state is always equal to the D input and it is independent of the present state. Therefore D must be 0 if Qn+1 have to 0, and if Qn+1 has to be 1 regardless the value of Qn.
18. Explain the flip- flop excitation tables for T flip-flop
When input T=1 the state of the flip- flop is complemented; when T=0,the state of the flip-flop remains unchanged. Therefore, for 0_0 and 1_1 transitions T must be 0 and for 0 1 and 1 0 transitions must be 1.
19. Define sequential circuit?
In sequential circuits the output variables dependent not only on the present input variables but they also depend up on the past history of these input variables.
20. Give the comparison between combinational circuits and sequential circuits.
S.No Combinational circuits Sequential circuits
1 Memory unit is not required Memory unity is required
2 Parallel adder is a combinational circuit Serial adder is a sequential circuit
Unit III
1. What are secondary variables?
Present state variables in asynchronous sequential circuits.
2. What are excitation variables?
Next state variables in asynchronous sequential circuits.
3. What is fundamental mode sequential circuit?
-input variables changes if the circuit is stable
-inputs are levels, not pulses
-only one input can change at a given time
4. What is pulse mode circuit?
-inputs are pulses
-widths of pulses are long for circuit to respond to the input -pulse width must not be so long that it is still present after the new state is reached
5. What is the significance of state assignment?
In synchronous circuits-state assignments are made with the objective of circuit reduction In Asynchronous circuits-its objective is to avoid critical races.
6. When does race condition occur?
Two or more binary state variables change their value in response to the change in i/p variable.
7. What is non-critical race?
-final stable state does not depend on the order in which the state variable changes. -race condition is not harmful
8. What is critical race?
-final stable state depends on the order in which the state variable changes
-race condition is harmful
9. When does a cycle occur?
Asynchronous circuit makes a transition through a series of unstable state.
10. What are the different techniques used in state assignment?
-shared row state assignment -One hot state assignment
11. What are the steps for the design of asynchronous sequential circuit?
-construction of primitive flow table
-reduction of flow table
-state assignment is made
-realization of primitive flow table
12. What is flow table?
It is defined as the state table of a synchronous sequential network.
13. What is primitive flow chart?
One stable state per row.
14. What is combinational circuit?
Output depends on the given input. It has no storage element.
15. What is state equivalence theorem?
Two states SA and SB are equivalent if and only if for every possible input X sequence, the outputs are the same and the next states are equivalent i.e., if SA ( t + 1) = SB (t + 1) and ZA = ZB then SA = SB.
16. What do you mean by distinguishing sequences?
Two states, SA and SB of sequential machine are distinguishable if and only if there exists at least one finite input sequence. Which, when applied to sequential machine causes different output sequences depending on whether SA or SB is the initial state.
17. Prove that the equivalence partition is unique.
Consider that there are two equivalence partitions exist: PA and PB, and PA PB. This states that, there exist 2 states Si &Sj which are in the same block of one partition and not in the same block of the other. If Si &Sj are in different blocks of say PB, there exists atleast on inputsequence which distinguishes Si &Sj and therefore, they cannot be in the same block of PA.
18. Define merger graph.
The merger graph is defined as follows. It contains the same number of vertices as the state table contains states. A line drawn between the two state vertices indicates each compatible state pair. It two states are incompatible no connecting line is drawn.
19. Explain the procedure for state minimization.
a. Partition the states into subsets such that all states in the same subsets are 1 -equivalent.
b. Partition the states into subsets such that all states in the same subsets are 2 -equivalent.
c. Partition the states into subsets such that all states in the same subsets are 3 -equivalent.
20. Define closed covering.
A Set of compatibles is said to be closed if, for every compatible contained in the set, all its implied compatibles are also contained in the set. A closed set of compatibles, which contains all the states of M, is called a closed covering.
Unit – IV
1. What is a Logic gate?
Logic gates are the basic elements that make up a digital system. The electronic gate is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical function.
2. Give the classification of logic families
1. Bipolar Unipolar
2. Saturated Non Saturated PMOS
3. NMOS
4. CMOS
5. RTL Schottky TTL
6. ECL DTL
7. TTL
8. I I C
3. What are the basic digital logic gates?
The three basic logic gates are:
AND gate
OR gate
NOT gate
4. Classify the logic family by operation?
The Bipolar logic family is classified into a) Saturatedlogic b) Unsaturated logic
The RTL, DTL, TTL, I2L, HTL logic comes under the saturated logic family.
The SchottkyTTL, and ECL logic comes under the unsaturated logic family.
5. State the classifications of FET devices.
FET is classified as
Junction Field Effect Transistor (JFET)
Metal oxide semiconductor family (MOS).
6. Mention the classification of saturated bipolar logic families.
The bipolar logic family is classified as follows:
1. RTL- Resistor Transistor Logic
2. DTL- Diode Transistor logic
3. I2L- Integrated Injection Logic
4. TTL- Transistor Transistor Logic
5. ECL- Emitter Coupled Logic
7. Mention the important characteristics of digital IC’s?
1. Fan out
2. Power dissipation
3. Propagation Delay
4. Noise Margin
5. Fan In
6. Operating temperature
7. Power supply requirements
8. Define Fan-out?
Fan out specifies the number of standard loads that the output of the gate can drive without impairment of its normal operation.
9. Define power dissipation?
Power dissipation is measure of power consumed by the gate when fully driven by all its inputs.
10. What is propagation delay?
Propagation delay is the average transition delay time for the signal to propagate from input to output when the signals change in value. It is expressed in NS.
11. Define noise margin?
It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an undesirable change in the circuit output. It is expressed in volts.
12. Define fan in?
Fan in is the number of inputs connected to the gate without any degradation in the voltage level.
13. What is Operating temperature?
All the gates or semiconductor devices are temperature sensitive in nature. The temperature in which the performance of the IC is effective is called as operating temperature. Operating temperature of the IC vary from 00 C to 700 c.
14. What is High Threshold Logic?
Some digital circuits operate in environments, which produce very high noise signals. For operation in such surroundings there is available a type of DTL gate which possesses a high threshold to noise immunity. This type of gate is called HTL logic or High Threshold Logic.
15. What are the types of TTL logic?
1. Open collector output
2. Totem-Pole Output
3. Tri-state output.
16. What is depletion mode operation MOS?
If the channel is initially doped lightly with p-type impurity a conducting channel exists at zero gate voltage and the device is said to operate in depletion mode.
17. What is enhancement mode operation of MOS?
If the region beneath the gate is left initially uncharged the gate field must induce a channel before current can flow. Thus the gate voltage enhances the channel current and such a device is said to operate in the enhancement mode.
18. Mention the characteristics of MOS transistor?
The n- channel MOS conducts when its gate- to- source voltage is positive.
The p- channel MOS conducts when its gate- to- source voltage is negative.
Either type of device is turned of if its gate- to- source voltage is zero.
19. How Schottky transistors are formed and state its use?
A schottky diode is formed by the combination of metal and semiconductor. The presence of Schottky diode between the base and the collector prevents the transistor from going into saturation. The resulting transistor is called as schottky transistor. The use of schottky transistor in TTL decreases the propagation delay without a sacrifice of power dissipation.
20. List the different versions of TTL
1. TTL (Std.TTL) 2.LTTL (Low Power TTL)
3. HTTL (High Speed TTL) 4.STTL (Schottky TTL)
5. LSTTL (Low power Schottky TTL)
UNIT V
1. List basic types of programmable logic devices.
a. Read only memory
b. Programmable logic Array
c. Programmable Array Logic
2. Define ROM
A read only memory is a device that includes both the decoder and the OR gates within a single IC package.
3. Define address and word:
In a ROM, each bit combination of the input variable is called on address. Each bit combination that comes out of the output lines is called a word.
4. What are the types of ROM?
a. Masked ROM.
b. Programmable Read only Memory
c. Erasable Programmable Read only memory.
d. Electrically Erasable Programmable Read only Memory.
5. What is programmable logic array? How it differs from ROM?
In some cases the number of don’t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM.
6. What is mask - programmable?
With a mask programmable PLA, the user must submit a PLA program table to the manufacturer.
7. What is field programmable gate array?
The second type of PLA is called a field programmable gate array. The EPLA can be programmed by the user by means of certain recommended procedures.
8. Give the comparison between prom and PLA.
S.No PROM PLA
1 And array is fixed and OR
array is programmable
Both AND and OR arrays are programmable.
2 Cheaper and simple to use Costliest and complex than PROMS
9. Define PROM.
PROM is Programmable Read Only Memory. It consists of a set of fixed AND gates connected to a decoder and a programmable OR array.
10. Define PLA
PLA is Programmable Logic Array (PLA). The PLA is a PLD that consists of a programmable AND array and a programmable OR array.
11. Define PAL
PAL is Programmable Array Logic. PAL consists of a programmable AND array and a fixed OR array with output logic.
12. Why was PAL developed?
It is a PLD that was developed to overcome certain disadvantages of PLA, such as longer delays due to additional fusible links that result from using two programmable arrays and more circuit complexity.
13. Why the input variables to a PAL are buffered
The input variables to a PAL are buffered to prevent loading by the large number of AND gate inputs to which available or its complement can be connected.
14. What does PAL 10L8 specify?
PAL - Programmable Logic Array
10 - Ten inputs
L - Active LOW Output
8 - Eight Outputs
15. Why totem pole outputs cannot be connected together.
Totem pole outputs cannot be connected together because such a connection might produce excessive current and may result in damage to the devices.
16. State advantages and disadvantages of TTL
Advantages:
Easily compatible with other ICs
Low output impedance
Disadvantages:
Wired output capability is possible only with tristate and open collector types Special circuits in Circuit layout and system design are required.
17. When does the noise margin allow digital circuit s to function properly?
When noise voltages ar e within the limits of VNA (High State Noise Margin) and VNK for a particular logic family.
18. Define state table.
For the design of sequential counters we have to relate present states and next states. The table, which represents the relationship between present states and next states, is called state table.
19. Define total state
The combination of level signals that appear at the inputs and the outputs of the delays define what is called the total state of the circuit.
20. What are the steps for the design of asynchronous sequential circuit?
1. Construction of a primitive flow table from the problem statement.
2. Primitive flow table is reduced by eliminating redundant states using the state reduction.
3. State assignment is made
4. The primitive flow table is realized using appropriate logic elements.
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