Anna Univ Chennai CS2207 Digital Laboratory Oct-Nov 2012 Question Paper

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ANNA UNIVERSITY : CHENNAI – 600 025
B.E/B.Tech Degree Examinations, Oct-Nov-2012
CS2207 Digital Laboratory
(B.E. Computer Science And Engineering)
Regulations - 2008
Time: 3 Hours Maximum Marks: 100

1. i) Verify the following Boolean algebra using logic gates (a)X+Y = Y+X (b)X+XY=X (c) X+ X
Y=X+Y [75 marks]
ii) ) Simulate De-Multiplexer using verilog Hardware Description Language [25 marks]

2. i) Verify the following expressions using Logic gates.(a)(X+Y)(X+Z)=X+YZ (b) (W+X)(Y+Z) = WY+WZ+XY+XZ (c) (XY)Z = XYZ [75 marks]
ii) Simulate 4 bit ripple counter using verilog Hardware Description Language [25 marks]

3. i ) Design a full adder circuit using logic gates . Construct the circuit and read output sum
and carry . Verify its truth table [75 marks]
ii) Simulate a Full adder using verilog Hardware Description Language . [25 marks]

4. i ) Design a combinational circuit that subtract 2 one bit binary numbers. Construct the circuit
using logic gates and observe output Difference and borrow. Verify its truth table [75 marks]
ii) Simulate 4 bit ripple counter using verilog Hardware Description Language [25 marks]

5. i) Design a BCD to Gray Code converter. Implement using logic gates and verify the output [75 marks]
ii) Simulate Multiplexer using verilog Hardware Description Language [25 marks]

6. i) Design BCD to Excess-3 code converter. Implement using Logic gates. Verify output [75 marks]
ii) Implement a De Multiplexer using verilog Hardware Description Language [25 marks]

7. i) Design a Excess-3 to BCD code converter. Implement and verify its truth table [75 marks]
ii ) Simulate 4 bit ripple counter using verilog Hardware Description Language [25 marks]

8. i) Design and implement a parity generator and checker using logic gates. Verify its operation [75 marks]
ii) Simulate a full adder using VHDL [25 marks]

9. i) Design a 4-bit binary adder and subtractor. Construct using suitable logic gates and verify its truth table. [75 marks]
ii) Simulate a adder using VHDL [25 marks]

10. i) Design a 4-bit binary adder and subtractor. Construct using suitable logic gates and verify
its truth table. [75 marks]
ii) Simulate a subtractor using VHDL [25 marks]

11. (i) Design and implement a magnitude comparator circuit to compare the relative magnitude
of two binary numbers . Verify its operation [75 marks]
(ii) Simulate a Full adder using VHDL . [25 marks]

12. (i) Design and implement a circuit to compare the relative magnitude of two binary numbers .
Verify its operation [75 marks]
(ii) Simulate a Full subtractor using VHDL . [25 marks]

13. i) Design and implement a multiplexer . Verify its operation using logic gates. [75 marks]
ii) Simulate the same multiplexer using VHDL [25 marks]

14. i) Design and implement a demultiplexer . Verify its operation using logic gates. [75 marks]
ii) Simulate the same demultiplexer using VHDL [25 marks]

15. i) Design a shift register . Conduct an experiment. Verify its operation [75 marks]
ii) Simulate the same shift register using VHDL. [25 marks]

16. i) Design a 4bit Synchronous up counter. Conduct an experiment. Verify its operation [75 marks]
ii) Simulate the same using VHDL. [25 marks]

17. i) Design a 4bit Synchronous down counter. Conduct an experiment. Verify its operation [75 marks]
ii) Simulate the same using VHDL. [25 marks]

18. i) Design a register that reads four bit data serially and writes four bit data serially. Construct and verify its truth table [75 marks]
ii) Simulate the same using VHDL. [25 marks]

19. i) Design a register that reads four bit data serially and writes four bit data simultaneously. Construct and verify its truth table [75 marks]
ii) Simulate the same using VHDL. [25 marks]

20. i) Design a circuit that select one of the several input lines and forward the selected input into single line. Verify its truth table experimentally. [75 marks]]
ii) Simulate the same using VHDL. [25 marks]

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