Looking for EE6301 / EE2255 DIGITAL LOGIC CIRCUITS May June 2014 Question Paper of B.E EEE Anna University Chennai ? You will be able to download here this question paper which comes under 03rd Semester in Regulation 2013. It was in 4th Semester for Regulation 2008 / 2009 and 2010. Read more details below and get your question paper.
Question Paper Code : 51439
Anna University Chennai
B.E / B.Tech DEGREE EXAMINATION, MAY / JUNE 2014.
Fourth Semester
Electrical and Electronics Engineering
EE2255 / EE 46 / EC 1261 A/ 080280029 / 10133 EE 406 A - DIGITAL LOGIC CIRCUITS [New Code: EE6301]
(Regulation 2008/2010)
(Common to PTEE 2255 Digital Logic Circuits for B.E (Part-Time) Third Semester Electrical and Electronics Engineering Regulation 2009)
Time : Three hours
Maximum : 100 marks
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Answer ALL questions.
PART A — (10 x 2 = 20 marks)
1. State De Morgan's theorem.
2. Give examples for weighted codes.
3. What is the drawback of SR flipflop?
4. What is a synchronous sequential circuit?
5. What is FPGA?
6. List the factors used for measuring the performance of digital logic families.
7. What is a turing machine?
8. What are the drawbacks in designing asynchronous sequential machines?
9. What are the advantages of hardware languages?
10. Write VHDL code for half adder in data flow model.
Question Paper Code : 51439
Anna University Chennai
B.E / B.Tech DEGREE EXAMINATION, MAY / JUNE 2014.
Fourth Semester
Electrical and Electronics Engineering
EE2255 / EE 46 / EC 1261 A/ 080280029 / 10133 EE 406 A - DIGITAL LOGIC CIRCUITS [New Code: EE6301]
(Regulation 2008/2010)
(Common to PTEE 2255 Digital Logic Circuits for B.E (Part-Time) Third Semester Electrical and Electronics Engineering Regulation 2009)
Time : Three hours
Maximum : 100 marks
Sponsored Link from Google:
Answer ALL questions.
PART A — (10 x 2 = 20 marks)
1. State De Morgan's theorem.
2. Give examples for weighted codes.
3. What is the drawback of SR flipflop?
4. What is a synchronous sequential circuit?
5. What is FPGA?
6. List the factors used for measuring the performance of digital logic families.
7. What is a turing machine?
8. What are the drawbacks in designing asynchronous sequential machines?
9. What are the advantages of hardware languages?
10. Write VHDL code for half adder in data flow model.
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