Are you looking for important questions of EE6301 Digital Logic Circuits ? You can here see the important questions of EE6301 Digital Logic Circuits for B.E EEE, EIE and ICE courses. This is one of the subjects of III Semester Regulation 2013 in Anna University Chennai. The exam of EE6301 Digital Logic Circuits commences on 30-11-2015. For well preparing this exam, refer the following important questions and practice them well to face your exams.
Anna University Chennai
Department of B.E EEE / EIE / ICE
Third Semester
EE6301 Digital Logic Circuits
November / December 2015 Exam Important Questions
(Regulation 2013)
1. Illustrate the basic principles of PLA and FPGA (16 marks)
2. Compare characteristics features of TTL, ECL, CMOS digital logic families (16 marks)
3. Write VHDL code for full adder and 8 x 1 multiplexer (16 marks)
4. Explain the different types of programmable logic devices with neat schematic and compare them (10 marks)
5. Write HDL for 4 bit binary counter with parallel load and explain
6. Write VHDL code for JK Master slave flipflops and using JK FF as structural element, write code for 4 bit Asynchronous counter (6+10 marks)
7. Draw an ECL AND Gate and explain (6 marks)
8. Write notes on ROM and its types (16 marks)
9. Design asynchronous BCD counter using JK flipflops (8 marks)
10. Design a 3 bit binary counter using T Flip Flop (8 marks)
11. Design 3 bit magnitude comparator (8 marks)
12. Prove that for constructing XOR from NANDs we need four NAND gates (8 marks)
You can also add up more questions by commenting below.
Anna University Chennai
Department of B.E EEE / EIE / ICE
Third Semester
EE6301 Digital Logic Circuits
November / December 2015 Exam Important Questions
(Regulation 2013)
1. Illustrate the basic principles of PLA and FPGA (16 marks)
2. Compare characteristics features of TTL, ECL, CMOS digital logic families (16 marks)
3. Write VHDL code for full adder and 8 x 1 multiplexer (16 marks)
4. Explain the different types of programmable logic devices with neat schematic and compare them (10 marks)
5. Write HDL for 4 bit binary counter with parallel load and explain
6. Write VHDL code for JK Master slave flipflops and using JK FF as structural element, write code for 4 bit Asynchronous counter (6+10 marks)
7. Draw an ECL AND Gate and explain (6 marks)
8. Write notes on ROM and its types (16 marks)
9. Design asynchronous BCD counter using JK flipflops (8 marks)
10. Design a 3 bit binary counter using T Flip Flop (8 marks)
11. Design 3 bit magnitude comparator (8 marks)
12. Prove that for constructing XOR from NANDs we need four NAND gates (8 marks)
You can also add up more questions by commenting below.
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