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Guru Nanak Dev University
B.C.A Computer Application
Principal of Digital Electronics
BCA Ist year
April 2010 Question paper
Time Allowed : 3 Hours
Maximum Marks : 100
Note: Attempt any five questions in all. All questions carry equal marks.
1. Discuss various features of TTL, STTL and CMOS families and give their transfer characteristics.[Marks 20]
2. (a) Discuss voltage divider biasing scheme.[Marks 10]
(b) Explain working of FETs.[Marks 10]
3. (a) Show that NAND gates are universal gates.[Marks 10]
(b) Design a half-adder using NAND gates only.[Marks 10]
4. Explain the working principle of any DAC converter.[Marks 20]
5. Discuss any microprocessor compatible ADC and its interfacing.[Marks 20]
6. Discuss one error detecting and error correcting code each.[Marks 20]
7. Discuss the address selection logic for a ROM chip. Draw read and write control timing diagram. Compare PROM and EPROM.
[Marks 20]
8. Discuss the working and truth table of J-K flip-flop. Give its limitation and suggest any solution.[Marks 20]
Guru Nanak Dev University
B.C.A Computer Application
Principal of Digital Electronics
BCA Ist year
April 2010 Question paper
Maximum Marks : 100
Note: Attempt any five questions in all. All questions carry equal marks.
1. Discuss various features of TTL, STTL and CMOS families and give their transfer characteristics.[Marks 20]
2. (a) Discuss voltage divider biasing scheme.[Marks 10]
(b) Explain working of FETs.[Marks 10]
3. (a) Show that NAND gates are universal gates.[Marks 10]
(b) Design a half-adder using NAND gates only.[Marks 10]
4. Explain the working principle of any DAC converter.[Marks 20]
5. Discuss any microprocessor compatible ADC and its interfacing.[Marks 20]
6. Discuss one error detecting and error correcting code each.[Marks 20]
7. Discuss the address selection logic for a ROM chip. Draw read and write control timing diagram. Compare PROM and EPROM.
[Marks 20]
8. Discuss the working and truth table of J-K flip-flop. Give its limitation and suggest any solution.[Marks 20]
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