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VII Semester B.Tech. (Reg./Sup./lmp. - Including Part Time) Degree
Examination, November 201 1
(2007 Admn.)
PT 2K6/2K6 EC 701 : MICRO ELECTRONICS TECHNOLOGY
Time : 3 Hours Max. Marks: 100
I. a) Brief the effects of dopants during oxidation. [Marks 5]
b) Give the evaluation procedure of the simple CVD System. [Marks 5]
c) Draw the schematic of a simple Bicmos inverter and explain its operation. [Marks 5]
d) Brief the latch up in CMOS circuits. [Marks 5]
e) Give the different encodings used in stick diagram representation for nMOS process. [Marks 5]
f) List the various )" based design rules adopted for the transistor in nMOS, PMOS and CMOS. [Marks 5]
g) Describe the short comings of producing thick field oxide as isolation. [Marks 5]
h) Write short notes on ballistic nano transistors. [Marks 5]
II. a) i) Write short notes on types of photo resists. [Marks 5]
ii) Explain with a schematic, the CZO Charlski growth method in detail. [Marks 10]
OR
b) i) Briefly describe the advantage and disadvantages of Atmosphere pressure
CUD of diectrics. [Marks 5]
ii) State the Hicks laws. Give the mechanism factors for determination of
the diffusion coefficient D. [Marks 10]
III. a) i) Derive the expression for lds in a nMOS transistor in the different regions
of operations. [Marks 10]
ii) Mention the types of nMOS transistors and give their output characteristics
and made the parameters. [Marks 5]
OR
b) i) Explain the nMOS Fabrication process with required figures. [Marks 10 ]
ii) Compare CMOS and bifdar technology. [Marks 5]
IV. a) i) Give the Stick diagram of the NAND gate using nMOS and CMOS design
style. [Marks 8]
ii) Write short notes on Pass transistors and transmission gates. [Marks 7]
OR
b) Give the nMOS implementation of Sum and Carry output of a half adder
circuit. Also draw the layout of the above circuits. [Marks 15]
V. a) i) Explain the SWAMI Process in detail. Draw necessary figures. [Marks 10]
ii) Compare simple shallow trench isolation process and deep trench isolation
process. [Marks 5]
OR
b) i) Explain the different SOI methods in device isolation. [Marks 10]
ii) Write about the ohms law in nanometer scaled devices. [Marks 5]
VII Semester B.Tech. (Reg./Sup./lmp. - Including Part Time) Degree
Examination, November 201 1
(2007 Admn.)
PT 2K6/2K6 EC 701 : MICRO ELECTRONICS TECHNOLOGY
Time : 3 Hours Max. Marks: 100
I. a) Brief the effects of dopants during oxidation. [Marks 5]
b) Give the evaluation procedure of the simple CVD System. [Marks 5]
c) Draw the schematic of a simple Bicmos inverter and explain its operation. [Marks 5]
d) Brief the latch up in CMOS circuits. [Marks 5]
e) Give the different encodings used in stick diagram representation for nMOS process. [Marks 5]
f) List the various )" based design rules adopted for the transistor in nMOS, PMOS and CMOS. [Marks 5]
g) Describe the short comings of producing thick field oxide as isolation. [Marks 5]
h) Write short notes on ballistic nano transistors. [Marks 5]
II. a) i) Write short notes on types of photo resists. [Marks 5]
ii) Explain with a schematic, the CZO Charlski growth method in detail. [Marks 10]
OR
b) i) Briefly describe the advantage and disadvantages of Atmosphere pressure
CUD of diectrics. [Marks 5]
ii) State the Hicks laws. Give the mechanism factors for determination of
the diffusion coefficient D. [Marks 10]
III. a) i) Derive the expression for lds in a nMOS transistor in the different regions
of operations. [Marks 10]
ii) Mention the types of nMOS transistors and give their output characteristics
and made the parameters. [Marks 5]
OR
b) i) Explain the nMOS Fabrication process with required figures. [Marks 10 ]
ii) Compare CMOS and bifdar technology. [Marks 5]
IV. a) i) Give the Stick diagram of the NAND gate using nMOS and CMOS design
style. [Marks 8]
ii) Write short notes on Pass transistors and transmission gates. [Marks 7]
OR
b) Give the nMOS implementation of Sum and Carry output of a half adder
circuit. Also draw the layout of the above circuits. [Marks 15]
V. a) i) Explain the SWAMI Process in detail. Draw necessary figures. [Marks 10]
ii) Compare simple shallow trench isolation process and deep trench isolation
process. [Marks 5]
OR
b) i) Explain the different SOI methods in device isolation. [Marks 10]
ii) Write about the ohms law in nanometer scaled devices. [Marks 5]
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