University Of Pune Question Paper
S.E. (Instrumentation and Control) (Semester – II) Examination, 2011
DIGITAL TECHNIQUES
(2003 Course)
Time : 3 Hours Max. Marks : 100
N.B. : i) Answers to the two Sections should be written in separate answer
books.
ii) Neat diagrams must be drawn wherever necessary.
iii) Figures to the right indicate full marks.
iv) Assume suitable data, if necessary.
SECTION – I
1. a) Convert the following : 8
i) (214)10 to octal
ii) (3FD)H to binary
iii) (0.582)H to decimal
iv) (3509)10 to hexadecimal.
b) Perform following arithmetic functions : 4
i) (19B9)16 + (C7E6)16 =
ii) (317)8 + (613)8 =
c) i) Convert gray code 101011 into its binary equivalent. 2
ii) Convert (592)10 to excess-3code. 2
OR
2. a) Do the following conversions. 8
i) (11101.11)2 to decimal number.
ii) (684)10 to hexadecimal number.
iii) (19.6)10 to binary number.
iv) (110011)2 into hexadecimal number.
b) i) Add (3F8)H and (5B3)H. 2
ii) Add (167)8 and (325)8. 2
c) Using Quine Mc Cluskey method simplify the following expression.
D = f (a, b, c, d) = ∑(0,1, 2, 3, 6, 7, 8, 9,14,15) . 4
P.T.O.
[3962] – 315 -2-
3. a) Convert the following : 8
i) SR flipflop to T flipflop
ii) JK flipflop to D flipflop.
b) i) Compare SRAM and DRAM
ii) Compare PROM and PLA. 8
OR
4. a) What is contact bounce phenomenon ? Explain how basic SR flipflop
constructed using NAND gate can be used to avoid contact bounce
phenomenon. 8
b) Write a note on PAL programming. 8
5. a) i) Compare synchronous counter and Asynchronous counter. 10
ii) Design divide by 6 counter using T flipflop.
b) Design MOD-22 counter by using IC 7493. Draw connection diagram and
explain the reset logic. 8
OR
6. a) Design nonsequential Synchronous counter for avoid lockout condition. 10
b) Design divide by 86 counter by using IC 7490. 8
SECTION – II
7. a) Implement the following function using 4 : 1 multiplexer
F = ∑m (0,1, 3, 4, 8, 9,15) . 8
b) In a multi digit display system explain the concept of trailing zero blanking
and leading zero blanking. 8
OR
-3- [3962] – 315
8. a) What is multiplexed display system ? What are the advantages and limitations
of it over a nonmultiplexed system ? 8
b) Design 4 : 16 decoder using two 3 : 8 decoders. 8
9. a) Explain different schemes for interfacing TTL to CMOS. 8
b) Write a note on Tristate logic. 8
OR
10. a) Draw the circuit diagram and explain the operation of 2 input TTL NAND
gate with totem pole output. 8
b) Explain the working of CMOS NOR and CMOS NAND gate with appropriate
circuit. 8
11. Design a digital clock that display seconds, minutes and hour. Show the detail
design along with IC’S selected. 18
OR
12. Generate the following pulse train, where the desired pulse train is 010111. 18
————————
B/
S.E. (Instrumentation and Control) (Semester – II) Examination, 2011
DIGITAL TECHNIQUES
(2003 Course)
Time : 3 Hours Max. Marks : 100
N.B. : i) Answers to the two Sections should be written in separate answer
books.
ii) Neat diagrams must be drawn wherever necessary.
iii) Figures to the right indicate full marks.
iv) Assume suitable data, if necessary.
SECTION – I
1. a) Convert the following : 8
i) (214)10 to octal
ii) (3FD)H to binary
iii) (0.582)H to decimal
iv) (3509)10 to hexadecimal.
b) Perform following arithmetic functions : 4
i) (19B9)16 + (C7E6)16 =
ii) (317)8 + (613)8 =
c) i) Convert gray code 101011 into its binary equivalent. 2
ii) Convert (592)10 to excess-3code. 2
OR
2. a) Do the following conversions. 8
i) (11101.11)2 to decimal number.
ii) (684)10 to hexadecimal number.
iii) (19.6)10 to binary number.
iv) (110011)2 into hexadecimal number.
b) i) Add (3F8)H and (5B3)H. 2
ii) Add (167)8 and (325)8. 2
c) Using Quine Mc Cluskey method simplify the following expression.
D = f (a, b, c, d) = ∑(0,1, 2, 3, 6, 7, 8, 9,14,15) . 4
P.T.O.
[3962] – 315 -2-
3. a) Convert the following : 8
i) SR flipflop to T flipflop
ii) JK flipflop to D flipflop.
b) i) Compare SRAM and DRAM
ii) Compare PROM and PLA. 8
OR
4. a) What is contact bounce phenomenon ? Explain how basic SR flipflop
constructed using NAND gate can be used to avoid contact bounce
phenomenon. 8
b) Write a note on PAL programming. 8
5. a) i) Compare synchronous counter and Asynchronous counter. 10
ii) Design divide by 6 counter using T flipflop.
b) Design MOD-22 counter by using IC 7493. Draw connection diagram and
explain the reset logic. 8
OR
6. a) Design nonsequential Synchronous counter for avoid lockout condition. 10
b) Design divide by 86 counter by using IC 7490. 8
SECTION – II
7. a) Implement the following function using 4 : 1 multiplexer
F = ∑m (0,1, 3, 4, 8, 9,15) . 8
b) In a multi digit display system explain the concept of trailing zero blanking
and leading zero blanking. 8
OR
-3- [3962] – 315
8. a) What is multiplexed display system ? What are the advantages and limitations
of it over a nonmultiplexed system ? 8
b) Design 4 : 16 decoder using two 3 : 8 decoders. 8
9. a) Explain different schemes for interfacing TTL to CMOS. 8
b) Write a note on Tristate logic. 8
OR
10. a) Draw the circuit diagram and explain the operation of 2 input TTL NAND
gate with totem pole output. 8
b) Explain the working of CMOS NOR and CMOS NAND gate with appropriate
circuit. 8
11. Design a digital clock that display seconds, minutes and hour. Show the detail
design along with IC’S selected. 18
OR
12. Generate the following pulse train, where the desired pulse train is 010111. 18
————————
B/
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