Dr.A.P.J.Abdul Kalam University BE LATERAL III SEM ALL BRANCH Digital Circuit & Design (CS222T) Dec - 2020 Question Paper

Dr.A.P.J.Abdul Kalam University

Bachelor of Engineering

Third Semester Main Examination, Dec-2020

Digital Circuit & Design (CS222T)

Branch-CS

Time: 3:00 Hrs Max Marks 70

Note: 1. Attempt any five questions.

          2. Each question carries equal marks.

          3. Assume suitable data if necessary & state them clearly.

Q.1 (a) Prove the following using De-Morgan’s Theorem  (A+B) (C+D) = (A+B) + (C+D)

(b) What do you understand by Universal Gate? Design all logic gates using NAND/NOR universal gates.

Q.2 (a) Explain the construction of full adder using two half adder.

(b) Explain Multiplexer and Demultiplexer circuits.

Q.3 (a) What is flip-flop? Explain working of R-S flip flop.

(b) What is Master-slave flip-flop? How race around condition is avoided in masterslave flip-flop?

Q.4 (a) What is shift register? Explain serial in parallel out shift register.

(b) Draw a 5 bit ring counter using J-K Flip flop and explain its working.

Q.5 (a) Draw and explain the VI characteristic of CMOS inverter.

(b) State and differentiate between ROM, PROM, EPROM, and EEPROM.

Q.6 (a) Plot the following expression in K-Map and minimize them.

i) 𝐴𝐵𝐶𝐷 +𝐴𝐵𝐶𝐷 ̅̅̅̅̅̅̅̅ + 𝐴𝐵̅𝐶 + 𝐴𝐵

ii) y = ∑ 𝑚 (7, 9, 10, 11, 12, 13, 14, 15)

(b) Design a BCD adder using logic gates.

Q.7 (a) Design MOD 6 counter using J K Flip flop.

(b) Compare RTL and DTL logic families.

Q.8 Write a short note oni) Programmable Logic Array (PLA)

ii) Synchronous and asynchronous counter

iii) T- Flip Flop

iv) Encoder and Decoder

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